This white paper identifies the key drivers behind the migration to 100G interfaces, and leverages the unique ability of FPGAs to implement this high-speed interface. Standards evolution for this protocol is crucial to defining common implementation, which ultimately provides the means for cost efficiencies through economies of scale in production of key cost components. Consolidation to common interface standards facilitates the simplicity of architecture and operations. Ethernet interfaces are well defined for 10/100/1000 Mbps and 10 Gbps, with standards currently in the draft phase for moving beyond 10 Gbps.