Uniting Disparate HDL, FPGA and PCB Design Flows
With today’s high-speed, high gate-count, high pin-count FPGAs the only constant in FPGA design is the changes that occur along the way, both at the interconnect level—to meet timing and loss requirements—and at the pin assignment stage within the FPGA itself. The great benefit of design flexibility offered by the FPGA is also one of the biggest nightmares for board designers. Companies would be wise to examine existing processes closely, ensuring that the significant flexibility and power offered by today’s FPGAs doesn’t becoming a doorway for potentially significant PCB implementation problems. Tools such as I/O Designer not only automate the schematic connectivity required for PCB layout and verification, but also document which signal connections are made to which device pins and indicate how these pins map to the original board-level bus structures. With the right software tools and close collaboration between the parallel paths of FPGA and PCB design, weeks can be trimmed from FPGA design and PCB implementation schedules, providing significant overall cost savings in the long term.
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