Let’s suppose that you are on an ASIC design team that has created the RTL associated with a new design. Let’s further suppose that your team has two synthesis tools available to you: one is based on a traditional RTL and/or physically-aware approach, while the other is based on a unique instance-centric and interconnect-centric technology.

Now, let’s assume that you run both synthesis solutions on your design, and you discover that the new instance-centric and interconnect-centric synthesis engine generates a higher-quality gate-level netlist that is optimized with connectivity in mind. When this netlist is fed to the place-and-route engine, the result is a 10% reduction in the area of the die. What would this mean to you? Actually, it can mean several things, including higher yield, higher reliability, higher performance, lower power consumption, and lower cost devices (in some cases, for example, there may be savings of more than $2.00 per die).

This paper first presents a variety of different design scenarios based on different design sizes at different technology nodes to evaluate the real effects of a 10% reduction in die area. Next, the paper introduces the various techniques that are employed by Synplicity’s state-of-the-art Synplify ASIC synthesis engine in order to achieve this reduction in silicon real estate. Also included are results from some real-world, taped-out devices.