With ever shrinking project timelines, it has become absolutely essential for IPs to be delivered with zero defects to SoC integrators. IP availability has always been the critical part of SoC timelines. The more mature the IP, the better it is for the SoC timelines. This paper dicusses the challenges involved to deliver a fully validated ‘zero defect’ IP with more emphasis on the effort to reduce the verification gap, defined as the difference between the ability to fabricate and the ability to verify. This paper addresses the planning part only and introduces the concept of a Unified Test Plan (UTP) and discusses in detail the use of the UTP to resolve the above-mentioned issues.