This application report motivates the way the DDR high-speed timing requirements are now going to be communicated to system designers. The traditional method of using data sheet parameters and simulation models is tedious. The system designer uses this information to evaluate whether timing specifications are met and can be expected to operate reliably.

Ultimately, the real question the hardware designer wants answered is “How do I hook
it up?” The method used here is different: TI solves the system timing problem once, and then a solution is communicated via direct PCB routing rules. This approach is particularly well-suited to the embedded JEDEC DDR memory interface because of the naturally constrained system solution set and industry standard components.