As programmable logic finds its way into avionics, communications and medical applications, designers face demands for increased reliability and safety over many of the traditional markets for FPGAs. In these high-reliability markets, there has long been concern over the effect of ionizing radiation on memory circuits. However, its impact on programmable logic is not widely understood. With the focus on reliability and safety in these markets, designers must quantify these risks and understand how differing FPGA technologies react in this environment. This paper helps designers understand the impact of single event upsets (SEUs), single event transients (SETs) and mitigation techniques.