Driven by the trend to smaller, lighter, and thinner consumer products, smaller package types have been developed. Indeed, packaging has become a key determinant for using or abandoning a device in a new design. This application note first defines the terms “flip chip” and “chip-scale package” and explains the technical development of wafer-level packaging (WLP) technology. Next it discusses practical aspects of using wafer-level packaged devices. Topics in that discussion include: determining the availability of flip-chip/UCSP packaging for a given device; identifying a flip chip/UCSP by its marking; the reliability of wafer-level packaged parts; and finding applicable reliability information. The document concludes with an outlook on future packaging developments, references to documents used in writing this application note, and links to additional literature that addresses topics not discussed here.