TTL "Burn Rate" for Xilinx CPLDs
The goal of this document is to familiarize logic designers that have previously not used programmable logic with the benefits of Xilinx CPLDs, and show how to go about translating existing TTL type logic into similar CPLD solutions. The basis of the discussion begins with a familiarity of 7400 style logic, which is actually comprised of many different variations. These families were phenomenally successful, and many designers still use them. However, greater integration, lower power, faster solutions and in general, less noisy designs can now be had with a substantial price reduction by using Xilinx CPLDs. But, first, some basics need to be covered.
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