Now it comes to the sub 65nm technology node, which should be the first generation of the immersion micro-lithography. And the brand-new lithography tool makes many optical effects, which can be ignored at 90nm and 65nm nodes, now have significant impact on the pattern transmission process from design to silicon. And this will result in big challenge to the optical proximity effect correction. For, with the shrinkage of the critical dimension of IC design, the error budget for the CD variation becomes much tighter. And to meet the requirement of the tight CD control, more optical effects need to be taken into account while using some calibrated process model to represent the real lithography process. In the whole industry, it is thought that, instead of sparse optical proximity correction, grid based model for optical proximity correction should be started to employ for sub 65nm technology node. Considering that sparse model and grid-based model adopting different algorithm, OPC engineers sometimes maybe need to do some translation work between the two kinds of model forms. This paper will demonstrate a procedure for the model form translation purpose.

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