Towards Full-chip Prediction of Yield-Limiting Contact Patterning Failure: Correlation of Simulated Image Parameters to Advanced Contact Metrology Metrics
Electrical failure due to incomplete contacts or vias has arisen as one of the primary modes of yield loss for 130 nm and below designs in manufacturing. Such failures are generally understood to arise from both random and systematic sources. The addition of redundant vias, where possible, has long been an accepted DFM practice for mitigating the impact of random defects. Incomplete vias are often characterized by having a diameter near the target dimension but a depth of less than 100% of target. Voltage Contrast (VC) SEM metrology biases the wafer to directly measure electrical conductivity after fill/polish, and can therefore easily discern a lack of electrical connection to the underlying conductor caused by incomplete photo, etch, or fill processing. SEM profile grading (PG) leverages the rich content of the secondary electron waveform to decipher information about the bottom of the contact. Several authors have demonstrated an excellent response of the Profile Grade to intentional defocus vectors. However, the SEM can only target discreet or single digit groupings of contacts, and therefore requires intelligent guidance to identify those contacts which are most prone to failure, enabling protection of the fab WIP.
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