Towards an Object-Oriented Design Methodology Using SystemVerilog
Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are more and more seriously considering language-based methodologies for parts of their designs. The introduction of the System Verilog (SV) language initiated a closer relationship between software and hardware descriptions and development tools. This paper presents synthesis recommendations and the corresponding synthesis methodology to develop object-oriented models with SV constructs for hardware system implementations.
Please disable any pop-up blockers for proper viewing of this Whitepaper.