Achieving faster Turn-Around-Time (TAT) is one of the most attractive objectives for the silicon wafer manufacturers despite the technology node they are processing. This is valid for all the active technology nodes from 130nm till the cutting edge technologies. There have been several approaches adopted to cut down the OPC simulation runtime without sacrificing the OPC output quality, among them is using stronger CPU power and Hardware acceleration which is a good usage for the advancing powerful processing technology. Another favorable approach for cutting down the runtime is to look deeper inside the used OPC algorithm and the implemented OPC recipe. The OPC algorithm includes the convergence iterations and simulation sites distribution, and the OPC recipe is in definition how to smartly tune the OPC knobs to efficiently use the implemented algorithm. Many previous works were exposed to monitoring the OPC convergence through iterations and analyze the size of the shift per iteration, similarly several works tried to calculate the amount of simulation capacity needed for all these iterations and how to optimize it for less amount. The scope of the work presented here is an attempt to decrease the number of optical simulations by reducing the number of control points per site and without affecting OPC accuracy. The concept is proved by many simulation results and analysis. Implementing this flow illustrated the achievable simulation runtime reduction which is reflected in faster TAT. For its application, it is not just runtime optimization, additionally it puts some more intelligence in the sparse OPC engine by eliminating the headache of specifying the optimum simulation site length.

Note: By clicking on the above link, this paper will be emailed to your TechOnline log-in address by Mentor Graphics.