As the number of transistors doubles almost every two years, the ability to use a flat approach for full chip
floorplanning is hindered by the capacity limitation of current electronic design automation (EDA) tools—even though the EDA tools have expanded their capacity.


In this paper, we will show a top-down hierarchical chip floorplaning methodology for a large system-on-chip (SoC) allowing the reuse of blocks in the same chip, as well as in different chips. We will show how the same hierarchical approach is applicable to smaller chips accelerating design closure.