Historically, implementation reference methodologies (iRMs) applied specifically to single IP blocks. iRMs ensured a consistent and predictable hardening of routes to performance, power and area (PPA) targets, and single-CPU execution presented reasonable cycle-times for design closure. The hardening of larger IP sub-systems that contain multiple processors, peripheral devices and bus fabric is a challenge created by ever-shrinking geometries.

This article will explore a new approach that leverages Magma’s top-down Talus ACC solution to implement a quad version of the ARM11 MPCore synthesizable processor. The article also examines the challenges of delivering a top-down iRM, and how one can continue to ensure that soft IP remains a competitive methodology for building increasingly large and complex SoCs.


Reprinted in its entirety from ARM IQ Vol. 6, No. 2, 2007