The emergence of affordable high-end FPGAs is making them the technology of choice for an increasing number of electronics products that previously were the exclusive domain of ASICs. Offering unprecedented levels of integration on a single chip, today’s programmable devices have widely expanded the size, scope, and range of applications that can now be deployed on them. To ensure a fast and efficient implementation of these advanced, feature rich FPGAs, designers need access to the latest in productivity enhancing electronic design automation (EDA) tools and methodologies. For years, hardware/software (HW/SW) co-verification has been commonly used to debug ASIC SoC designs. Now, with embedded processors such as the PowerPC405 from IBM, combined with multi-million gate capacities commonplace in Virtex series FPGAs, there is an increased relevance for ASIC-strength methodologies such as co-verification to add value in the FPGA design space.

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