To Retain or Not to Retain: How Do I Verify the State Elements of My Low Power Design?
With power becoming a critical design constraint in the design environment, designers are utilizing advanced techniques to minimize power consumption in their designs. As a result, the RTL design is being extended to express the functionality of new cell types including retention cells, level shifters, and isolation cells. Some of these cells act like buffers powered by different supplies. Others, such as retention cells, can have complex functionality that requires specific sequences of control signals to achieve correct behavior. Traditionally, designers have had to explicitly specify the insertion of these cells, either with wrappers around existing RTL blocks, or through simulation command files that mimic their expected behavioral impact. Using command scripts to mimic behavioral implications creates real challenges in verifying the desired functionality: after incorporating all of the power-aware features, one cannot be sure that what is simulated is the same as what will be implemented. This paper will discuss the various challenges related to state verification of low power designs. We will describe mechanisms by which a designer can easily automate the complex process of managing the state elements in a low power design. A Power Aware Verification flow and tool is described that automatically detects the registers, latches, and memories present in the user’s RTL. The power intent is separately specified using the Unified Power Format (UPF). We will illustrate easy-to-use techniques to map specific retention behaviors to particular registers. We will also show how the tool automates the burden of connecting power and logic control signals to the verification models – thus automating this tedious task.
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