To Interleave, or Not to Interleave: That is the Question
With the emergence of multi-gigabit-persecond SERDES bus architectures such as PCI Express, Xilinx RocketIO technology has become a vital part of FPGA designs. But accompanying these faster buses is a resurgence of an old design problem: crosstalk. The source of concern is similar to what occurs in buses like PCI and PCI-X: a large number of signals all need to go to the same place, from the FPGA to a connector or to another chip.
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