TLM2 in SystemVerilog
Transaction-level modeling (TLM) is a methodology for building models at high levels of abstraction, those above RTL. TLM-2.0 is a library that contains classes that implements a methodology for building transaction-level models and connecting them together. TLM-2.0 was written in SystemC that implements a particular transaction-level methodology. It was developed by OSCI and released in 2009 and is now on its way to becoming an IEEE standard as part of the IEEE-1666-2011. In order to support new use models in SystemVerilog, a translation of TLM-2.0 is now included in UVM. This paper will describe the translation of TLM-2.0 from SystemC to SystemVerilog.
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