Many of the chipsets today used in modern electronics from LCD TV’s to mobile phones are developed in state-of-the-art technologies well below 130nm. These technologies have a minimal tolerance to DC voltages over 3.3V so an ESD pulse can be catastrophic for such a device. Furthermore, requirements for “on-board” or “on-chip” ESD protection have been lowered to 500V, well below the typical field requirement of 8kV. Therefore, board designers not only need external ESD protection, but they also need to make sure it’s robust enough given the vulnerability of the small geometry chipsets. This white paper addresses various techniques a board designer can employ to help him/her attain the ESD level required for their design should the chosen ESD protection devices fail in-system ESD testing.