The tools available in Altera’s Quartus II development software are designed to help address the challenges that effect timing closure—the availability of critical resources, the amount of routing congestion both local and global, and the ability to accurately time the logic to avoid timing volitions that could otherwise be caused by skews within the clock network—but often simple HDL changes will go a long way towards resolving timing issues and reducing the time it takes to achieve timing closure. This white paper addresses these possible HDL changes and their relationship to the architecture and layout of the FPGA.