Timing Considerations When Using NVSRAM
Dallas Semiconductor’s NVSRAM modules are constructed using a Dallas nonvolatile controller, a low-power CMOS Static RAM memory component, and a lithium coin-cell battery. Under normal operating conditions, read or write operations are functionally identical to a stand-alone SRAM. Using the parallel I/O structure, a user can easily store data to, or fetch data from any memory location defined by the address bus width. This application note assists in preparing the system memory timing for use with Dallas Semiconductor’s Nonvolatile SRAM (NVSRAM).
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