Timing Closure 6.1i
The high performance of today’s Xilinx devices can
overcome the speed limitations of other technologies and older devices. Furthermore, designs that formerly only fit or ran at high clock frequencies in an ASIC are finding their way into Xilinx FPGAs. However, it is imperative that designers have a proven methodology for obtaining their performance objectives.
This paper has been written specifically to address timing closure in high-performance applications. Consider its guidelines a road map for improving performance and meeting timing objectives. Similar to a road map, you may find detours, different and faster paths, and newer roads that will help you to achieve your goals.
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