As the technology node is shrinking, the timing closure challenges across PVT corners are becoming more and more difficult. This challenge accentuates even more for analog-digital interfaces like ADC for which we need to meet many such timing requirements which are not standardized. This paper talks about some specific timing requirements, timing closure challenges and mitigation techniques experienced by the designers in some recent SoCs involving ADC. However, these design considerations may be applicable to other similar analog-digital interfaces as well and would help SoC Engineer in timely and error free implementation and timing signoff.