This paper describes the new requirements that FPGA design software must satisfy to quickly and efficiently perform timing analysis and achieve timing closure. (For the purpose of this paper, timing analysis and static timing analysis are the same tasks performed with the same static tools. For brevity’s sake, we will refer simply to timing analysis.) Productivity requirements include the adoption of an industry-standard timing analysis methodology, and this white paper will illustrate a few practical applications of the industry-standard Synopsys Design Constraints (SDC) format. Additionally, productivity is enhanced by integrating the timing analysis engine with the place-and-route engine.