A methodology of advanced process window simulations with awareness of chip topology is presented. This method identifies the expected focal range encountered due to different topology in different areas within a design. As a result, respective defocus models are used to drive the LFD simulations and detect CD (Critical Dimension) variations in printing features. By building process models to be implemented, we can attempt to pinpoint process hotspots based on where they would appear on a real wafer. Identified hotspots are then compared to real wafer results, and a practical use of these results is fed to OPC. Finally all hotspots are enhanced by OPC with applied focus shifting instead of design revision.

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