Thermal Limits of Flip Chip Package—Experimentally Validated
This study projects the thermal performance limits of a flip chip package. A plastic, Pin Grid Array (PGA) package with Direct Chip Attach (DCA) interconnect was chosen for the demonstration purpose. Same methodology as developed here can be applied to other flip chip packages. The design rules chosen are the allowable power dissipation for constraints of junction temperature (<105°C) and board temperature (-<90*C) under either free air or forced air (1.27 m/s) condition. Experiments were performed with a thermal test chip in a flip chip package. Results indicated that the enhanced package (with heat sink and thermal pad) performed 3 times (in terms of junction*to-ambient thermal resistance) better than the basic package (no heat sink, no thermal pad) in free air and 6 times better in 1.27 m/s of air. It was also found that the inclusion of underfill did not enhance the package thermal performance significantly. The exact experimental environment was modeled using a Computational Fluid Dynamics (CFD) tool. Computational results indicated a good agreement between simulation and the experimental data with an average difference of less than 6%. The validated CFD model was used to predict the thermal performance limits of the flip chip package. Simulations were run by increasing the power to the package under consideration until either the junction temperature or the board temperature reached its limit. Based on these constraints, the allowable power dissipation in the package was determined to be between 1.7 and 6.7 W in free air and between 2.1 and 13.7 W in 1.27 m/s of air. The validated CFD models offer enormous potential to quickly asses thermal limits of many future flip chip packages and their variations.
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