In several applications, it is sometimes necessary to convert a signal from one sample rate to another. An input can be downsampled before processing to ease the computational load, or sometimes two units must be connected whose respective sample rates do not match. If the desired sample-rate is an integer multiple of the existing one, it is sufficient to oversample the input using an interpolation filter. Likewise, if the existing sample-rate is an integer multiple of the one you want out, you can employ decimation or undersampling. However, if the ratio between input and output sample-rate is an arbitrary number, matters become more complicated. An arbitrary sample rate converter, or ASRC, must be designed. In such systems, the input and output signals are often derived from two separate clocks as well, in which case the conversion must be done using an asynchronous (arbitrary) sample rate converter (AASRC).

This document will give an introduction to the principles of arbitrary sample rate conversion and how to model it. Performance issues as well as the AASRCs suitability as a “jitter-killer” will also be examined.