The Target Platform Methodology for HW/SW Debugging Before Silicon
Design teams today push the envelope with large, complex designs containing many functional components. They must tackle complexity, throughput, latency, cost, battery lifetime and time-to-market issues for successive product versions. Adding to the challenge is the necessity of rapid product development in a highly competitive market.
With verification as the major element of product development, verification time savings directly accelerates delivery to customers. Many designers are adopting emulation with a target platform as their primary verification methodology. This methodology allows them to ensure that their software is ready and debugged before the chip comes back from the foundry. This paper describes the three major verification methodologies available today: emulation as a verification foundation; emulation with a target platform approach; and mapping of SystemC transaction level models (TLM) into the emulator.
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