The increase in size and complexity of many of today’s high-speed wireless and video algorithms has driven the need for a design methodology that provides designers with a rapid path from creating algorithms in C++ to RTL running in hardware. With their rapidly growing capacity and dedicated arithmetic hardware, platform field programmable gate arrays (FPGAs) have become an attractive and cost-effective solution for addressing the massive parallelism required by these algorithms. This white paper will focus on the FPGA features of Catapult C, and how close integration with Precision RTL maintains the amazing productivity gains of the algorithmic C++ synthesis design flow.

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