Nanometer technology drives complexity not just in IC design, but also the processes used to create IC designs. The progressive reduction in feature size enables dramatically higher circuit densities and the integration of mixed signal blocks. This, in turn, demands EDA solutions with advanced capabilities, that offer a more simplified, integrated flow; a “glue” that provides the cohesive framework of an SoC. Varied point tools were once sufficient to handle designs at larger process nodes; today, platforms are emerging as the solution for meeting the demands of designers in the nanometer era.

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