The forward march of Moore’s Law has resulted in integrated circuit (IC) designs containing more and more functionality on a single chip. While new technology enables expanded capability, such as analog mixed signal systems-on-chip (AMS SoC), it brings with it a new set of design closure problems. These complex designs demand more power and higher clock frequencies; they also create more signal and power net electromigration and substrate noise. If these parasitic effects are not accurately handled, a single cell can cause an entire design to fail. This is a huge problem not only for designers, as the failure rate of designs at first silicon is now as high as 80%, but also for design companies, as costly re-spins can result in lost market opportunities and mask costs reach $1 million each.

At larger process technologies, parasitic extraction could be handled by using tools employing simple cell characterization at the gate level and/or an assumptive method of measuring physical parameters. But with the advanced functionality and small design sizes of 130nm process technology, assumptive parametric measurement and gate level extraction are no longer enough to solve the ever-increasing amounts of parasitic problems or to gain accurate mixed-level simulation. Neither is it enough to just add a basic transistor-level parasitic extraction tool to the flow. Irregularly shaped diffusion and stress effects not considered in the design phase can result in failed designs.

Typical work-around solutions are no longer workable. With costs of chip manufacturing and failure rates at first silicon at all time highs, designers cannot afford to overlook the effects of parasitics on the bottom line. Yet without comprehensive, accurate data, proper analysis and simulation of AMS SoCs is nearly impossible.

Engineers need new, efficient and comprehensive methods of ensuring working analog mixed signal designs. By adopting a full-chip parasitic extraction tool that is seamlessly integrated with a robust LVS tool, accurate gate- and transistor- and multi-level extraction and post-layout simulation becomes possible.

Note: By clicking on the above link, this paper will be emailed to your TechOnLine log-in address by Mentor Graphics.