SoC type devices contain a large number of processors and accelerators working in front of many memory arrays ranging from off-chip “static” data storage to on die L1/L2/L3 caches. With an increase in the number of memory arrays, there is also a demand to lower the devices power consumption; a complicated task in memory arrays that are already optimized as far as current technologies may be exploited. Putting the power consumption as priority number one, minimizing it can be achieved by lowering response time or larger die size. This may be a price worth paying, depending on the application, thus giving way to a new cell design.