This paper explains how the technologies and methodologies underlying the Mentor Graphics 0-In Formal Verification (FV) tool facilitate practical formal verification of IC functionality. 0-In Formal Verification includes the 0-In Search, 0-In Confirm, and 0-In Prove engines and uses assertion-based verification (ABV) to accelerate the discovery and diagnosis of design flaws during the verification process. The differences between the Mentor Graphics 0-In FV tool and FV tools supplied by other vendors are also described.

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