A 100Gbps coherent receiver needs four 56GSa/s Analog-to-Digital Converters (ADCs) and a tera-OPS DSP that dissipates only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution. The paper also introduces the Fujitsu ultra-fast CMOS ADC, which provides the enabling technology for 100Gbps Ethernet and OTU-4 transport systems using coherent receivers.