As programmable logic devices (PLDs) increase in density and complexity, the combination of a feature-rich fabric and sophisticated design tools enables users to realize their performance goals in less time. Shorter design cycle times enable users to lower overall design costs and meet time-to-market requirements. This white paper highlights how the Virtex-II Pro™ FPGA and ISE6 design tool combination provides a 40% performance advantage over the nearest competitor, the Altera Stratix™ PLD.