Taxonomy of Functional Verification for Virtual Component Development and Integration
In the semiconductor industry, there is tremendous momentum in using in-house or third-party developed virtual components (VCs) to create new hardware design. These designs vary from system-on-chip (SoC) to some bridge or multi-peripheral device. The biggest challenge is to verify the functionality of the virtual component in different chip designs, in different physical implementations, and in different development environments. There are a number of tools, techniques, and methodologies used to accomplish the functional verification of the virtual component and the system.
This document is intended to provide a classification of the various verification technologies and uniform definitions of terms used in these technologies. It is the first of a series of documents and specifications from the Functional Verification Development Working Group (DWG). Other releases on the DWG roadmap will document verification deliverables and “best practices” for verification, as well as extend into other areas of verification above the functional level.
The intended audience for this document includes design and verification engineers involved in the creation of VCs as well as those engineers who are integrating VCs and verifying SoC designs containing VCs. At the end of Section 1, Section 2, and Section 3, definitions of terms used in each section are listed. At the end of the document, there is a summary of all the definitions in alphabetical order.
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