Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only results in increased resource utilization, but also challenges existing tools, flows and techniques.

Adding on-demand signoff-quality design rule checks (DRC) verification inside place and route (P&R) tools during digital implementation provides immediate feedback on targeted window-based DRC fixes. P&R engineers can spend less time running batch DRC, so they can focus on producing high-quality, optimized designs.

Fixing a G0 violation may require multiple iterations. With instantaneous feedback using selected check groups, engineers can fix an error quickly.

Download the Free Whitepaper on DRC Verification Tools: