Algorithmic synthesis tools use a true top-down DSP design methodology that enables a collaborative design effort between algorithm developers, system engineers and hardware designers. Synthesis tools facilitate this by directly reading in MATLAB models and automatically creating synthesizable RTL models and simulation testbenches in VHDL or Verilog. This paper focuses on the tool capabilities that DSP and hardware designers can use to automatically evaluate potential implementation options during early design stages and rapidly make design tradeoffs, leading to a low-risk methodology that produces the most cost-effective designs while meeting design specifications.