Tackling I<sup>2</sup>C Development Complexities Using Innovative Tools
Validating device compliance to the I2C protocol is a difficult task. Understanding how a device reacts under non-ideal conditions such as stress testing is even tougher. This paper describes an I2C bus analysis tool that helps ease I2C bus compliance and interoperability with unique features such as parametrics testing, glitch injection, timing skew, and master/slave emulation.
Please disable any pop-up blockers for proper viewing of this Whitepaper.