SystemC Modeling Synthesis and Verification in Catapult C
Catapult C Synthesis added SystemC support for modeling, verification, and synthesis of complex ASICs at the system level. Both cycle-accurate and transaction-level (TLM) abstractions are supported, addressing SoC-specific needs such as bus interfaces and interconnects as well as connections with ESL flows. This Catapult flow promotes abstraction and design reuse. This paper gives an overview and a detailed example of SystemC support in Catapult.
Please disable any pop-up blockers for proper viewing of this Whitepaper.