System Verilog and OVM: Mitigating Verification Challenges and Maximizing Reusability
This paper explains how to accomplish an ideal verification platform for our designs using System Verilog and a standard methodology (OVM), plus some in-house ideas that helped us to make a more practical and easy-to-use verification environment. The challenges spanned right from configuring the components, injecting the transactions to create various test scenarios, phasing of the test cases till the end of report generation etc. This paper also explains how SV and OVM has simplified a whole lot in controlling the messaging policy, sequences and sequencers layering, OOPs data patterning to fit certain environment architecture requirements, barrier mechanism to overcome OVM phasing limitations and ready-made harness system for the sub-system integration, making things simpler and organized.
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