As the complexity of system-on-chip (SoC) devices rises to include scores, in some cases hundreds, of distinct blocks, system validation becomes a critical concern. A variety of techniques have emerged to help designers verify that individual blocks of a device meet performance specifications, but validating functional intent in a system context is a relatively new challenge for hardware designers.

This article outlines an approach for high-level system validation before RTL implementation, and presents a flow to achieve this increasingly essential task.

Reprinted in its entirety from ARM IQ Vol. 5, No. 2, 2006