System-level Debugging in a Multi-core Wireless Virtual System Prototype
Developing a complex multi-core wireless system is a major challenge, especially when the cores include both a high-performance processor and a leading-edge digital signal processor (DSP). Waiting until hardware prototypes are available is unacceptable: important hardware/software tradeoffs must be made long before the chips are fabricated. The traditional approach has been to rely on instruction-set simulator (ISS) models for the cores to perform pre-silicon verification and debugging. Unfortunately, ISS models can be too slow and lack the timing accuracy needed to interact with the RTL models for the hardware portion of the system.
The problem is worse in a multi-core environment, since individual emulator tools often lack synchronization mechanisms in debug mode. The result is that some aspects of the software development and hardware/software integration must wait until the wireless hardware prototypes are ready. The process of development and debugging on expensive, scarce hardware prototypes delays project schedules and increases the risk of chip turns.
This whitepaper presents a method for system-level debugging of a multi-core system using a virtual system prototype, which allows a cycle-accurate simulation of a complete system to execute in real time on a PC. This is a much faster solution than ISS-based simulation. Complete system-level single-stepping can be performed, providing the debug mode a level of timing accuracy that matches the real-world setup. Further, virtual system prototypes provide flexibility during development by enabling developers to experiment quickly and accurately over multiple system setups and scenarios. An example of a multi-core wireless system containing two ARM processors and a StarCore DSP demonstrates the effectiveness of this approach.
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