The expressive power of SystemVerilog assertions (SVA) with local variables enables specification of complex properties in a concise form (for example, properties involving data integrity). However, using local variables might result in unacceptable performance during simulation or formal verification if proper precaution is not taken when coding assertions.


This paper provides a set of coding guidelines and a methodology for efficient SVAlocal variable use. The guidelines allow one to take advantage of the expressiveness of SVAlocal variables while avoiding pitfalls that can result in reduced performance and capacity.

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