Cyclone III phase-locked loops (PLLs) are feature rich, supporting advanced capabilities such as clock switchover, dynamic phase shifting, and PLL reconfiguration. Previously, PLLs in Altera Cyclone FPGAs were designed to be configured for a specific input frequency. The newly added voltage-controlled oscillator (VCO) range detector in Cyclone III PLLs, together with the dynamic phase reconfiguration and PLL reconfiguration, enable the support for advanced display applications where the PLL input frequency may not be known ahead of time or may change. In this “unknown FREF video application,” the initial input frequency to the PLL is 60 MHz to 80 MHz, varying from
15 MHz to135 MHz in later stages.

This paper presents a reference design that targets a video application that uses x7 mode low-voltage differential signaling (LVDS). To support the x7 mode LVDS interface, the PLL output frequencies are set to 0.5X, 1X, and 3.5X of input frequency.