Sub-threshold leakage is a major component of dissipation in lower technology nodes and can contribute significantly to the total dissipation, at elevated temperatures. The only effective way, to eliminate leakage is, to switch off the transistors, when not required. When the logic is ON, transistors would leak, no matter what. There is, therefore, a need to reduce the sub-threshold leakage, emanating from the dynamic affects of the design. Transistor leakage is conventionally believed to be a frequency independent phenomenon. This paper studies the indirect affect of frequency on the leakage of a design and proposes some techniques to control leakage.