Exorbitant and growing ASIC mask costs require customers to engage in extensive and expensive verification. Designers can expect a full 90 nm mask set to cost $1M, but this is only a small portion of the estimated ~$25M development cost of an ASIC. About half of the overall ~$25M is devoted to verification tools and engineering intended to increase the likelihood that silicon “works right, first time” and to avoid spending an indeterminate amount of time on analysis and money on masks. Unfortunately a majority of ASIC designs today require respins.