New process technologies enable IC devices of extreme sizes and complexity; SoC designs incorporate whole systems on a single chip. Yet as complexity increases, the time to get these devices to market continues to shrink. The demand for reduced iterations and decreased time-to-market results in the need to uncover and fix potential manufacturing problems, such as antenna effects and lithography aberrations, earlier during the physical design cycle. A physical verification and analysis flow needs to provide accurate solutions for these challenges, reduce the number of iterations involved in verifying a chip, and provide the fastest possible performance.

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