Traditionally, digital logic has not consumed significant static power, but this has changed with very small process nodes. Leakage current in digital logic is now the primary challenge for FPGAs as process geometries decrease. While the move to the 65-nm process delivers the expected Moore’s law benefits of increased density and performance, the performance increases can result in significant increases in power consumption. This introduces the risk of consuming unacceptable amounts of power. Learn how the Stratix III solution provides the performance designers need at the lowest possible power of any high-end FPGA.

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