Stratix III FPGA Signal Integrity
As devices move towards faster switching speed and higher pin counts, signal and power integrity become crucial, making or breaking a system. Chip designs that work perfectly for 90-nm process technology may no longer be good enough for a 65-nm chip. Poor signal integrity causes poor reliability, degrades system performance, and, worst of all, system failures. Numerous enhancements have been implemented on Stratix III FPGAs to improve signal and power integrity performance over the previous generation Stratix II family. These include die- and package-level signal return paths optimized with an 8:1:1 user I/O to ground/power ratio to reduce loop inductance, an improved decoupling scheme, dynamic on-chip termination (OCT), programmable LVDS buffer, and new control features for slew rate and staggered output delay that enable the designer to control the noise level of the device.
This white paper discusses how the new features and enhancements of Altera Stratix III FPGAs address these issues and benefit customers’ systems by improving signal and power integrity and simplifying printed circuit board (PCB) design.
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